Periodic signals are used in a variety of electronic devices. One type of periodic signal are clock signals that can be used to establish the timing of a signal or the timing at which an operation is performed on a signal. For example, data signals are typically coupled to and from memory, such as synchronous dynamic random access memory (“SDRAM”), in synchronism with a clock or data strobe signal. More specifically, read data signals are typically coupled from a memory in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal should have a phase that is the quadrature (having a phase 90-degrees relative to the phase) of the write data signals so that a write data strobe signal transitions during a “data eye” occurring at the center of the period in which the write data signals are valid.
Internal clock signals generated in electronic devices, for example, memory devices or memory controllers, are often synchronized or have some other controlled phase relationships relative to external or internal clock signals. For example, with reference to a memory, a quadrature clock signal used for both latching write data and outputting read data may be generated in the memory to which the data are being written. The quadrature clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal.
Internal clock signals having synchronized or some other controlled phase relationships with external and internal clock signals may also be used for applications other than for use as a write data strobe signal. For example, a “frequency doubler” circuit, which generates an output clock signal having twice the frequency of an input clock signal, can be implemented using an appropriate logic circuit that receives the input clock signal and quadrature versions of the input signal. Internal signals may also be generated having other than a quadrature phase relationships. Generally, any phase relationship between output clock signals can be used.
Various techniques can be used to generate a quadrature clock signals or read/write data strobe signal. If the frequency of the internal clock signal is fixed, quadrature clock signals may be generated by a timing circuit that simply generates a transition of the quadrature clock signals a fixed time after a corresponding transition of the internal clock signal. However, synchronous memory are typically designed and sold to be operated over a wide range of clock frequencies. Therefore, it is generally not practical to use a fixed timing circuit to generate quadrature clock signals from the internal clock signal. Instead, a circuit that can adapt itself to an internal clock signal having a range of frequencies must be used.
An example of such a circuit is a multi-phase clock signal generator. A multi-phase clock signal generator, as known, generates multi-phase clock signals to provide several clock signals having fixed phase relationships to a reference clock signal, such as an external or internal clock signal. A multi-phase clock signal generator typically includes a multi-tap adjustable delay line that is used to delay and divide phase relationships within the reference clock signal. The multi-tap adjustable delay line is fine-tuned until the phase of a delayed clock signal from the adjustable delay line is in-phase with a reference signal. Generally, multi-phase signals are “tapped” from the adjustable delay line having equal delays relative to one another. The result is provision of several multi-phase clock signals having pre-defined phase relationships with one another. Phases are typically divided evenly within one or a number of reference clock periods. For example, two-phase, triple-phase, quadrature-phase or five-phase are typical choices.
The multi-phase clock signals provided by the multi-phase clock signal generator, however, generally have the same duty-cycle distortion as the reference clock signal. That is, if the reference clock signal exhibits a distorted duty-cycle, by virtue of the reference clock signal being propagated through a series of delay elements of the adjustable delay line, the multi-phase clock signals will have a similar distorted duty-cycle. A clock period is considered as having a duty-cycle distortion when there is deviation from a clock pulse of 50 percent. In some applications, for example in a memory or other types of electronic systems where power supply noise and clock jitter with severe duty-cycle distortion may be present, it is desirable to generate high-speed, duty-cycle corrected multi-phase clock signals over a wide frequency range and that have high accuracy. Additionally, generating multi-phase clock signals in high-speed systems present additional challenges. For example, in such applications it is desirable for multi-phase clock signal generators to generate multi-phase clock signals having highly accurate phase relationships, operate at high-speed and over wide frequency ranges, provide fast robust initialization, have tolerance to wide reference clock duty-cycle distortion, and provide accurate duty-cycle correction capability. It is additionally desirable for the multi-phase clock signal generators to have relatively low power consumption and have limited circuit layout cost.
Therefore, there is a need for multi-phase clock signal generators providing multi-phase clock signals having corrected duty-cycles.